A Variation-Tolerant Processing-In-Memory Architecture Using Discharging Current Calibration
Author:
Affiliation:
1. Renesas Electronics Corporation,Tokyo,Japan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9980472/9980536/09980781.pdf?arnumber=9980781
Reference5 articles.
1. A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2;okumura;VLSI Circ Symp,2019
2. A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC
3. A Hybrid In-Field Self-Test Technique for SoCs
4. A machine-learning classifier implemented in a standard 6T SRAM array;zhang;VLSI Circ Symp,2016
5. Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices
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