FPGA implementation of FIR filters using pipelined bit-serial canonical signed digit multipliers-Reference-Cited by-同舟云学术

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FPGA implementation of FIR filters using pipelined bit-serial canonical signed digit multipliers

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Container-title:Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94
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Author:

He S.,Torkelson M.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx2/3036/8629/00379762.pdf?arnumber=379762

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Phase-orthogonal FIR filters: An efficient VLSI architecture for communication applications;IEICE Electronics Express;2020-07-25

2. Design and Realization of High-Speed and Real-Time Signal Processing System Based on FPGA;Applied Mechanics and Materials;2011-10

3. Efficient implementation of 90° phase shifter in FPGA;EURASIP Journal on Advances in Signal Processing;2011-07-28

4. Design and Implementation of a Scalable Channel Emulator for Wideband MIMO Systems;IEEE Transactions on Vehicular Technology;2009-11

5. A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 m Standard CMOS Library;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2007-07-01

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