Adaptive DFE Utilizing Fixed Step Error Signal for Multi-Gb/s Serial Links
Author:
Affiliation:
1. Utah Valley University,Department of Electrical and Computer Engineering,Orem,Utah,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10099037/10098906/10099051.pdf?arnumber=10099051
Reference14 articles.
1. A 0.2–2 Gb/s 6x OSR Receiver Using a Digitally Self-Adaptive Equalizer
2. New 2-D Eye-Opening Monitor for Gb/s Serial Links
3. A 10-Gb/s eye-opening monitor IC for decision-guided adaptation of the frequency response of an optical receiver
4. A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS
5. A scalable 3.6-5.2 mW 5-to-l0Gb/s 4-tab DFE in 32 nm;chen;IEEE Int'l Solid-State Circuits Conf Dig Tech Papers,2009
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