Process Variation's Effect on Various Threshold Voltage Assignments in 6T SRAM Designs Using 12nm FinFET Technology
Author:
Affiliation:
1. Ulkasemi Private Limited,Circuit and System Design Department,Dhaka,Bangladesh
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10099037/10098906/10099370.pdf?arnumber=10099370
Reference7 articles.
1. SRAM devices and circuits optimization toward energy efficiency in multi-Vth CMOS
2. Ultra-Low Power, Process-Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications
3. Subthreshold SRAM: Challenges, design decisions, and solutions
4. Maximization of SRAM energy efficiency utilizing MTCMOS technology
5. Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation;nho;Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation IEEE Transactions on Circuits and Systems II Express Briefs,2008
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1. Power Optimization in 6T-SRAM Cell using Carbon Nanotube Field-Effect Transistors (CNTFET);2023 7th International Conference on Electronics, Communication and Aerospace Technology (ICECA);2023-11-22
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