A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical Stress-Reference-Cited by-同舟云学术

A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical Stress

Published:2023-05-01 Issue:5 Volume:72 Page:1447-1459
ISSN:0018-9340
Container-title:IEEE Transactions on Computers
language:
Short-container-title:IEEE Trans. Comput.

Author:

Angione Francesco¹^ORCID,Appello Davide²,Bernardi Paolo¹^ORCID,Bertani Claudia²,Gallo Giovambattista¹,Littardi Stefano¹,Pollaccia Giorgio²,Ruggeri Walter¹^ORCID,Reorda Matteo Sonza¹^ORCID,Tancorre Vincenzo²^ORCID,Ugioli Roberto²

Affiliation:

1. Politecnico di Torino, Torino, Italy

2. STMicroelectronics, Agrate Brianza, Italy

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://xplorestaging.ieee.org/ielx7/12/10094223/09861726.pdf?arnumber=9861726

Reference45 articles.

1. Survey of Test Vector Compression Techniques

2. Test Integration for SOC Supporting Very Low-Cost Testers

3. Modular automatic test equipment design for on-platform diagnostics

4. TestosterICs: a low-cost functional chip tester

5. Wafer Level Stress: Enabling Zero Defect Quality for Automotive Microcontrollers without Package Burn-In

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1. A New High-efficient Burn-in Screening Methodology Applied in Automotive Integrated Circuits Reliability;2023 24th International Conference on Electronic Packaging Technology (ICEPT);2023-08-08

2. A New Numerical Algorithm to Estimate the Average Travel Time of Workpiece in Packaging Equipments or Reliability Testers;2023 24th International Conference on Electronic Packaging Technology (ICEPT);2023-08-08

3. A Toolchain to Quantify Burn-In Stress Effectiveness on Large Automotive System-on-Chips;IEEE Access;2023