Design Challenges and Techniques for 5nm FinFET CMOS Analog/Mixed-Signal Circuits
Author:
Affiliation:
1. NXP Semiconductors,India
2. Western Digital,India
3. Intel Corporation,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10089791/10089793/10089917.pdf?arnumber=10089917
Reference13 articles.
1. Gate length scaling and threshold voltage control of double-gate MOSFETs
2. Design and process technology co-optimization with SADP BEOL in sub-10nm SRAM bitcell
3. A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects
4. A spacer patterning technology for nanoscale CMOS
5. An inverter layout technique for propagation delay minimization
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