A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers-Reference-Cited by-同舟云学术

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A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers

Published:2001 Issue:2 Volume:36 Page:204-216
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Yan W.S.T.,Luong H.C.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/19525/00902761.pdf?arnumber=902761

Cited by 23 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Novel Design of High Performance Low Power Phase-Frequency Detector for CMOS PLL Frequency Synthesizer;International Journal of Sensors, Wireless Communications and Control;2020-12

2. New dual-loop topology for ring VCOs based on latched delay cells;2018 IEEE International Symposium on Circuits and Systems (ISCAS);2018

3. Frequency Synthesis Based on A Novel Differential Locking Mechanism;2018 IEEE International Symposium on Circuits and Systems (ISCAS);2018

4. A frequency multiplier for reference frequency in frequency synthesizer systems;Analog Integrated Circuits and Signal Processing;2017-11-29

5. A novel technique for duty cycle correction for reference clocks in frequency synthesizers;Microelectronics Journal;2017-09

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