Cost-Efficient Solution to Overcome Latch-Up Path in 5 V-Tolerant I/O With Low-Voltage Biased NBL Isolation Ring in a 0.18-μm BCD Technology
Author:
Affiliation:
1. Institute of Pioneer Semiconductor Innovation, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
2. Institute of Electronics and the Institute of Pioneer Semiconductor Innovation, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
Funder
National Science and Technology Council (NSTC), Taiwan
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/16/10457976/10399373.pdf?arnumber=10399373
Reference15 articles.
1. Latch-Up in CMOS Integrated Circuits
2. Latchup
3. Transient-Induced Latchup in CMOS Integrated Circuits
4. Chip level layout and bias considerations for preventing neighboring I/O cell interaction-induced latch-up and inter-power supply latch-up in advanced CMOS technologies;Huh
5. Study on Latchup Path between HV-LDMOS and LV-CMOS in a 0.16-μm 30-V/1.8-V BCD Technology
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1. Latch-up Risk in 5V-tolerant I/O Buffer Surrounded by NBL Isolation Ring with Low-Voltage Bias;2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA);2024-04-22
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