Low-Frequency Noise in InGaAs-OI Transistors
Author:
Affiliation:
1. Department of Electronics, Nanoelectronics Research Group (CITIC-UGR), University of Granada, Granada, Spain
2. IBM Research Zurich, Ruschlikon, Switzerland
Funder
Consejería de Universidad, Investigación e Innovación and ERDF Andalusia Program
European Union NextGeneration EU/PRTR through Spanish Projects
European Project REMINDER
MSCA TRAPS-2D
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/16/10538150/10517983.pdf?arnumber=10517983
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1. Device scaling limits of Si MOSFETs and their application dependencies
2. Retrospective on VLSI value scaling and lithography
3. High-k/metal gates-from research to reality;Narayanan
4. Engineered substrates for Moore and more than Moore's law: Device scaling: Entering the substrate era
5. Forksheet FETs for advanced CMOS scaling: Forksheet-nanosheet co-integration and dual work function metal gates at 17 nm N-P space;Mertens
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