Design Of Wallace Multiplier Using Novel Approximate 4:2 Compressors
Author:
Affiliation:
1. V.R. Siddhartha Engineering College,Department of Electronics and Communication,Vijayawada,India,520007
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10135544/10136027/10136063.pdf?arnumber=10136063
Reference19 articles.
1. Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands
2. Variable latency speculative addition
3. IMPACT: IMPrecise adders for low-power approximate computing
4. A low latency generic accuracy configurable adder
5. Low power, high speed approximate multiplier for error resilient applications;skandha;Integration the VLSI Journal,2020
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1. Low Power CMOS based 4-2 Compressor Architecture Using XOR-XNOR and Multiplexers;2024 3rd International Conference on Computational Modelling, Simulation and Optimization (ICCMSO);2024-06-14
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