An FPGA-based High-Throughput Packet Classification Architecture Supporting Dynamic Updates for Large-Scale Rule Sets-Reference-Cited by-同舟云学术

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An FPGA-based High-Throughput Packet Classification Architecture Supporting Dynamic Updates for Large-Scale Rule Sets

Published:2021-05-10 Issue: Volume: Page:
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Container-title:IEEE INFOCOM 2021 - IEEE Conference on Computer Communications Workshops (INFOCOM WKSHPS)
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Author:

Xin Yao,Li Wenjun,Wang Yi,Yao Song

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9484327/9484428/09484440.pdf?arnumber=9484440

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. FATSS: Filter-Assisted Tuple Space Search for Packet Classification;2022 IEEE International Performance, Computing, and Communications Conference (IPCCC);2022-11-11

2. FACL: A Flexible and High-Performance ACL engine on FPGA-based SmartNIC;2022 IFIP Networking Conference (IFIP Networking);2022-06-13

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