Offset Voltage Reduction Methods for a Two-Stage Folded Cascode Operational Amplifier
Author:
Affiliation:
1. University Politehnica of Bucharest,Faculty of Electronics, Telecommunications and Technology Information,Bucharest,Romania
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9847306/9847307/09847308.pdf?arnumber=9847308
Reference9 articles.
1. Analog Circuit Design - Course Notes;st?nescu;Faculty of Electrical Engineering and Information Technology University “Politehnica” of Bucharest,0
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3. The impact of MOSFET's physical parameters on its threshold voltage;zabeli;Proceedings of the 6th WSEAS International Conference on Microelectronics Nanoelectronics Optoelectronics,2007
4. Dynamic Offset Compensated CMOS Amplifiers
5. Matching properties of MOS transistors
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