Parasitic Effects Analysis and Equivalent Circuit Modeling of Tapered Serpentine Interconnects of On-chip FBAR up to 67GHz
Author:
Affiliation:
1. Southwest University of Science and Technology,School of Information Engineering,Mianyang,China,621010
2. East China Jiaotong University,School of Information Engineering,Nanchang,China,330013
Funder
National Natural Science Foundation of China
Natural Science Foundation of Sichuan Province
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10616250/10617814/10618097.pdf?arnumber=10618097
Reference11 articles.
1. SBCT-NoC: Ultra Low-Power and Reliable Simultaneous Bi-directional Current-mode Transceiver for Network-on-Chip interconnects
2. Modified Knowledge-Based Neural Networks Using Control Variates for the Fast Uncertainty Quantification of On-Chip MWCNT Interconnects
3. Structure Fortification of Mixed CNT Bundle Interconnects for Nano Integrated Circuits Using Constraint-Based Particle Swarm Optimization
4. Stochastic Wave-Pipelined On-Chip Interconnect
5. Knowledge-Based Neural Networks for Fast Design Space Exploration of Hybrid Copper-Graphene On-Chip Interconnect Networks
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