Improved Power Density of a 6 kV, 1 MW Power Electronics Building Block Through Insulation Coordination
Author:
Affiliation:
1. Center for Power Electronics Systems (CPES), Virginia Polytechnic Institute and State University (Virginia Tech),Blacksburg,VA,USA
Funder
U.S. Office of Naval Research
ARPA-E
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9829904/9829946/09829968.pdf?arnumber=9829968
Reference11 articles.
1. Design and Multiobjective Optimization of an Auxiliary Wireless Power Transfer Converter in Medium-Voltage Modular Conversion Systems
2. Design of a Multilayer PCB Bus for Medium Voltage DC Converters
3. Insulation Design and Optimization of Laminated Busbar for More Electric Aircraft Motor Drive under High Altitude and Depressurized Environments;yuan;2020 AIAA/IEEE Electric Aircraft Technologies Symposium (EATS),2020
4. A High-Speed Gate Driver with PCB-Embedded Rogowski Switch-Current Sensor for a 10 kV, 240 A, SiC MOSFET Module
5. High Power Density Medium-Voltage Converter Integration via Electric Field Management
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3. Practical Insulation Testing of 10 kV SiC MOSFET Modules;2023 IEEE Energy Conversion Congress and Exposition (ECCE);2023-10-29
4. Modeling of Conducted EMI Emissions in 10 kV SiC MOSFET Based Power Electronics Building Blocks;2023 IEEE Energy Conversion Congress and Exposition (ECCE);2023-10-29
5. Thermal Management Approaches for Power Electronic Building Blocks and Power Corridors;2023 IEEE Electric Ship Technologies Symposium (ESTS);2023-08-01
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