FPGA implementation of efficient FIR Filter with quantized fixedpoint coefficients-Reference-Cited by-同舟云学术

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FPGA implementation of efficient FIR Filter with quantized fixedpoint coefficients

Published:2013-10 Issue: Volume: Page:
ISSN:
Container-title:2013 International Conference on Emerging Trends in Communication, Control, Signal Processing and Computing Applications (C2SPCA)
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Author:

Bhalke Santosh,Manjula B.M. ,Sharma Chirag

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6739910/6749343/06749406.pdf?arnumber=6749406

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Power-Efficient Multichannel Low-Pass Filter Based on the Cascaded Multiple Accumulate Finite Impulse Response (CMFIR) Structure for Digital Image Processing;Circuits, Systems, and Signal Processing;2022-02-10

2. Pipelined Distributive Arithmetic-based FIR Filter Using Carry Save and Ripple Carry Adder;2021 2nd International Conference on Communication, Computing and Industry 4.0 (C2I4);2021-12-16

3. Field Programmable Gate Array (FPGA)-Based Fast and Low-Pass Finite Impulse Response (FIR) Filter;Intelligent Computing and Innovation on Data Science;2020

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