A Comprehensive Investigation of $\text{GaSb}/\text{GaAs}_{0.5}\text{Sb}_{0.5}/\text{GaAs}$ based Double Gate Source-Pocket Engineered Heterogeneous Gate Dielectric Vertical TFET for Optimized Low-Power Applications
Author:
Affiliation:
1. Military Institute of Science and Technology,Department of Electrical, Electronic and Communication Engineering,Dhaka,Bangladesh
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10534252/10534311/10534541.pdf?arnumber=10534541
Reference19 articles.
1. Design Trade-offs in Ultra-Low-Power Digital Nanoscale CMOS
2. Performance Comparison Between p-i-n Tunneling Transistors and Conventional MOSFETs
3. Two-dimensional analytical modeling of the surface potential and drain current of a double-gate vertical t-shaped tunnel field-effect transistor
4. Temperature-Dependent $I$– $V$ Characteristics of a Vertical $\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ Tunnel FET
5. Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and ≪60mV/dec subthreshold slope
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