Design of Power-Efficient Configurable Booth Multiplier
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/8919/5424135/05061521.pdf?arnumber=5061521
Cited by 34 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Bit-Separable Radix-4 Booth Multiplier for Power-Efficient CNN Accelerator;2024 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS);2024-04-17
2. Design of a Novel Inexact 4:2 Compressor and Its Placement in the Partial Product Array for Area, Delay, and Power-Efficient Approximate Multipliers;Circuits, Systems, and Signal Processing;2024-03-16
3. A STT-Assisted SOT MRAM-Based In-Memory Booth Multiplier for Neural Network Applications;IEEE Transactions on Nanotechnology;2024
4. Performance evaluation of low power reconfigurable multiplier architectures using different adders for signal processing applications;AIP Conference Proceedings;2024
5. Programmable All-in-One 4×8-/2×16-/1×32-Bits Dual Mode Logic Multiplier in 16 nm FinFET With Semi-Automatic Flow;IEEE Access;2023
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