Author:
Goumas G.,Athanasaki M.,Koziris N.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Computational Theory and Mathematics,Hardware and Architecture,Signal Processing
Cited by
16 articles.
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1. Optimizing Tiled Matrix-Matrix Product According to Cache Performance Enhancement;2018 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Ubiquitous Computing & Communications, Big Data & Cloud Computing, Social Computing & Networking, Sustainable Computing & Communications (ISPA/IUCC/BDCloud/SocialCom/SustainCom);2018-12
2. An Overview on Loop Tiling Techniques for Code Generation;2017 IEEE/ACS 14th International Conference on Computer Systems and Applications (AICCSA);2017-10
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5. Parameterized Diamond Tiling for Stencil Computations with Chapel parallel iterators;Proceedings of the 29th ACM on International Conference on Supercomputing;2015-06-08