Signal Processing Architecture for Real-time Earthquake Early Warning System
Author:
Affiliation:
1. Indian Institute of Technology Kharagpur,Department of Electronics and Electrical Communication Engineering,Kharagpur,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10176201/10176203/10176234.pdf?arnumber=10176234
Reference24 articles.
1. Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal
2. Rapid Assessment of Damage Potential of Earthquakes in Taiwan from the Beginning of P Waves
3. A trigonometric formulation of the LMS algorithm for realization on pipelined CORDIC
4. VLSI Implementation of A Robust Threshold-Based Earthquake Early Warning System
5. An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth
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