An Efficient Exponential Unit Designed in VLSI CMOS with Custom Operators-Reference-Cited by-同舟云学术

An Efficient Exponential Unit Designed in VLSI CMOS with Custom Operators

Published:2022-10-24 Issue: Volume: Page:
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Container-title:2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
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Author:

da Costa Patricia¹,da Rosa Morgana²,Paim Guilherme¹,da Costa Eduardo³,Soares Rafael²,Bampi Sergio¹

Affiliation:

1. Graduate Program on Microelectronics (PGMICRO) - Federal University of Rio Grande do Sul (UFRGS),Porto Alegre,Brazil

2. Graduate Program on Computing - Federal University of Pelotas (UFPel),Pelotas,Brazil

3. Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel),Pelotas,Brazil

Funder

CNPq

Capes

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9970762/9970770/09970960.pdf?arnumber=9970960

Reference12 articles.

1. A fixed point exponential function accelerator for a neuromorphic many-core system

2. FPGA based implementation of low-latency floating-point exponential function;yuan;IET International Conference on Smart and Sustainable City 2013 (ICSSC 2013),0

3. Hardware Efficient Architecture for 2D DCT and IDCT Using Taylor-Series Expansion of Trigonometric Functions

4. SECO: A Scalable Accuracy Approximate Exponential Function Via Cross-Layer Optimization

5. A Fixed-Point Natural Logarithm Approximation Hardware Design Using Taylor Series

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