Effect of Equalization Bandwidth and Linearity on NRZ and PAM4 Eye Diagram
Author:
Affiliation:
1. NXP Semiconductors,Chandler,AZ,USA
2. Analog and Mixed-Signal Center, Texas A&M University,College Station,TX,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9970762/9970770/09970913.pdf?arnumber=9970913
Reference8 articles.
1. A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS
2. Optimal PAM Order for Wireline Communication
3. A 5.4 Gbps Type-C USB3.1/DP1.2 Combo Limiting ReDriver in $0.14\ \mu\mathrm{m}$ CMOS Technology;delshadpour;2019 IEEE Canadian Conference of Electrical and Computer Engineering (CCECE),0
4. A 20.6 Gb/s Programmable Peaking Gain CTLE
5. Low Power 20.625 Gbps Type-C USB3.2/DP1.4/ Thunderbolt3 Combo Linear Redriver in $0.25\ \mu\mathrm{m}$ BiCMOS Technology;delshadpour;2018 31st IEEE International System-on-Chip Conference (SOCC),0
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1. Equalization for Compensation of Intersymbol Relationship of Multi-Valued Signaling Using Two-Dimensional Symbol Mapping;2024 IEEE 54th International Symposium on Multiple-Valued Logic (ISMVL);2024-05-28
2. Equalization technology and Quantization analysis for Data-converter Based PAM4 SerDes Link;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20
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