Hardware Acceleration of a Fully Parallel Viterbi Decoder Architecture for Narrow Band IOT
Author:
Affiliation:
1. German University in Cairo,Faculty of Information Engineering and Techology,Egypt
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9970762/9970770/09970985.pdf?arnumber=9970985
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4. An optimal circular Viterbi decoder for the bounded distance criterion
5. A High-throughput Parallel Viterbi Algorithm via Bitslicing;khalaj monfared;ACM Trans Parallel Comput,2021
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