Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators
Author:
Affiliation:
1. Politecnico di Milano,DEIB,Milano,Italy
2. SIAE MICROELETTRONICA,Milano,Italy
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9970762/9970770/09970992.pdf?arnumber=9970992
Reference18 articles.
1. Flexible and Scalable FPGA-Oriented Design of Multipliers for Large Binary Polynomials
2. Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum Cryptography
3. Efficient and scalable FPGA design of GF(2m) inversion for post-quantum cryptosystems
4. On the use of hardware accelerators in QC-MDPC code-based cryptography
5. Fast Polynomial Inversion for Post Quantum QC-MDPC Cryptography
Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. FPGA-Based Design and Implementation of a Code-Based Post-quantum KEM;SpringerBriefs in Applied Sciences and Technology;2024
2. HLS-based acceleration of the BIKE post-quantum KEM on embedded-class heterogeneous SoCs;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04
3. RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project;Lecture Notes in Computer Science;2023
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