High-throughput FFT architectures using HLS tools
Author:
Affiliation:
1. Bordeaux-INP, Univ. of Bordeaux,IMS Laboratory (CNRS UMR 5218),France
2. ARELIS (LGM Group),Saint-Aubin-lès-Elbeuf,France
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9970762/9970770/09970886.pdf?arnumber=9970886
Reference19 articles.
1. FFT/IFFT implementation using Vivado™ HLS
2. Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA Devices
3. Model-based Design of Hardware SC Polar Decoders for FPGAs
4. Radix-8 FFT processor design based on FPGA
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