A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS
Author:
Affiliation:
1. The University of Shiga Prefecture,Hikone,Shiga,Japan,522-8533
2. Gifu University,Gifu,Japan,501-1193
Funder
National Institute of Information and Communications Technology
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9970762/9970770/09970848.pdf?arnumber=9970848
Reference7 articles.
1. DC wander effect of DC blocking capacitors on PCIe Gen3 signal integrity
2. A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks
3. A 10G/1G dual-rate burst-mode receiver for next generation optical access networks;nogawa;NTT Technical Review,2014
4. A 10/2.5-Gb/s Hyper-Supplied CMOS Low-Noise Burst-Mode TIA with Loud Burst Protection and Gearbox Automatic Offset Cancellation for XGS-PON
5. A dual‐rate burst‐mode receiver with rapid response and high CID tolerance for XGS PON
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