Design of High-speed Serial data Generation Module with Controllable Edge Jitter Based on Phase Interpolation

Author:

Yang Wanyu,Liang Chao,Zhou Jianmin

Funder

Fundamental Research Funds for the Central Universities

National Key R&D Program of China

Publisher

IEEE

Reference17 articles.

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2. Research on spur Source and reduction based on Direct Digital Frequency synthesizer [J];qun;Wireless Internet Technology,2016

3. Variable delay of multi-gigahertz digital signals for deskew and jitter-injection test applications[C];keezer;Design Automation and Test in Europe,2008

4. Periodic jitter injection with direct time synthesis by SPPtm ATE for serdes jitter tolerance test in production[C];shimanouchi;International Test Conference,0

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