Author:
Ghiye Vikram,Bonde Sharan,Dhande Ashwinikumar
Cited by
4 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Speed-Area-Power Efficient Ternary Logic Gate Implementation Based on Typical MOS Transistors;2024 International Conference on Electronics, Information, and Communication (ICEIC);2024-01-28
2. DPL-based novel CMOS 1-Trit Ternary Full-Adder;International Journal of Electronics;2020-07-09
3. DPL-based novel time equalized CMOS ternary-to-binary converter;International Journal of Electronics;2019-09-11
4. Utilization of Karnaugh Maps in Multi-Value Qualitative Comparative Analysis;International Journal of Mathematical, Engineering and Management Sciences;2018-03-01