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Extended MASTAR Modeling of DIBL in UTB and UTBB SOI MOSFETs

  • Published:2012-01 Issue:1 Volume:59 Page:247-251
  • ISSN:0018-9383
  • Container-title:IEEE Transactions on Electron Devices
  • language:
  • Short-container-title:IEEE Trans. Electron Devices

Author:

Arshad Mohd Khairuddin Md,Raskin Jean-Pierre,Kilchytska Valeriya,Andrieu François,Scheiblin Pascal,Faynot O.,Flandre Denis

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Cited by 25 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Characterization of fully silicided source/drain SOI UTBB nMOSFETs at cryogenic temperatures;Solid-State Electronics;2022-06

2. Performance Analysis of a Double-Gate Junctionless Transistor with Varied Doping and Gate Underlap using Device Simulator;2021 IEEE International Conference on Sensors and Nanotechnology (SENNANO);2021-09-22

3. Impact of the Backgate on the Performance of SOI UTBB nMOSFETs at Cryogenic Temperatures;2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS);2021-09-01

4. Analog Figures of Merit of Vertically Stacked Silicon Nanosheets nMOSFETs With Two Different Metal Gates for the Sub-7 nm Technology Node Operating at High Temperatures;IEEE Transactions on Electron Devices;2021-07

5. Strategy for Simulation of Analog Circuits with GCSOI MOSFET using BSIM SOI model;2021 IEEE Latin America Electron Devices Conference (LAEDC);2021-04-19
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