Multi-objective layout optimization for Multi-Chip Power Modules considering electrical parasitics and thermal performance-Reference-Cited by-同舟云学术

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Multi-objective layout optimization for Multi-Chip Power Modules considering electrical parasitics and thermal performance

Published:2013-06 Issue: Volume: Page:
ISSN:
Container-title:2013 IEEE 14th Workshop on Control and Modeling for Power Electronics (COMPEL)
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Author:

Shook Brett W.,Nizam Andalib,Gong Zihao,Francis A. Mathew,Mantooth H. Alan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6605719/6626389/06626450.pdf?arnumber=6626450

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Review of Hybrid Packaging Methods for Power Modules;Chinese Journal of Electrical Engineering;2023-12

2. Automatic Layout Design and Implementation for Three Phase Voltage Source Converters;2023 IEEE Design Methodologies Conference (DMC);2023-09-24

3. Automatic Design of a Busbar in SiC Controller;Key Engineering Materials;2023-07-31

4. A Multi-Objective, Machine-Learning-Based Optimization Method and its Application to a Power Card Package Design;2023 IEEE Transportation Electrification Conference & Expo (ITEC);2023-06-21

5. Graph-Model-Based Generative Layout Optimization for Heterogeneous SiC Multichip Power Modules With Reduced and Balanced Parasitic Inductance;IEEE Transactions on Power Electronics;2022-08

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