Low Temperature and Ion-Cut Based Monolithic 3D Process Integration Platform Incorporated with CMOS, RRAM and Photo-Sensor Circuits

Author:

Han Hoonhee,Choi Rino,Jung Seong-Ook,Chung Sung Woo,Cho Byung Jin,Song S. C.,Choi Changhwan

Publisher

IEEE

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Formation techniques for upper active channel in monolithic 3D integration: an overview;Nano Convergence;2024-01-29

2. Small Footprint 6T-SRAM Design with MIV-Transistor Utilization in M3D-IC Technology;2023 IEEE 41st International Conference on Computer Design (ICCD);2023-11-06

3. FDSOI Process Based MIV-transistor Utilization for Standard Cell Designs in Monolithic 3D Integration;2023 IEEE 36th International System-on-Chip Conference (SOCC);2023-09-05

4. Efficient and Scalable MIV-Transistor with Extended Gate in Monolithic 3D Integration;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06

5. Metal Inter-layer Via Keep-out-zone in M3D IC: A Critical Process-aware Design Consideration;2023 24th International Symposium on Quality Electronic Design (ISQED);2023-04-05

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