INVITED PAPER: A 4.5-5.4GHz Digital Bang-Bang PLL for Cryogenic Applications
Author:
Affiliation:
1. Fudan University,Shanghai,China
2. ShanghaiTech University,Shanghai,China
3. Shanghai Institute of Microsystem and Information Technology,Chinese Academy of Sciences,Shanghai,China
4. The University of Tokyo,Tokyo,Japan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10363774/10363775/10364251.pdf?arnumber=10364251
Reference17 articles.
1. Implicit Common-Mode Resonance in LC Oscillators
2. Temperature-Driven Gate Geometry Effects in Nanoscale Cryogenic MOSFETs
3. 9.8 An 860μW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications
4. A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH $\Delta \Sigma $ -TDC for Low In-Band Phase Noise
5. Enhanced Jitter Analysis and Minimization for Digital PLLs With Mid-Rise TDCs and its Impact on Output Phase Noise
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