Charge-recovery power clock generators for adiabatic logic circuits-Reference-Cited by-同舟云学术

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Charge-recovery power clock generators for adiabatic logic circuits

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Container-title:18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
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Author:

Arsalan M.,Shams M.

Publisher

IEEE Computer Soc

Link

http://xplorestaging.ieee.org/ielx5/9501/30140/01383272.pdf?arnumber=1383272

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A ±0.5-mV-Minimum-Input DC-DC Converter With Stepwise Adiabatic Gate-Drive and Efficient Timing Control for Thermoelectric Energy Harvesting;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-02

2. Scalable Resonant Power Clock Generation for Adiabatic Logic Design;2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2021-07

3. Analysis of stepwise charging limits and its implementation for efficiency improvement in switched capacitor DC–DC converters;Analog Integrated Circuits and Signal Processing;2021-03-04

4. Investigating the influence of adiabatic load on the 4-phase adiabatic system design;Integration;2020-11

5. Design of Adiabatic Logic-Based Energy-Efficient and Reliable PUF for IoT Devices;ACM Journal on Emerging Technologies in Computing Systems;2020-07-31

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