On test time reduction using pattern overlapping, broadcasting and on-chip decompression-Reference-Cited by-同舟云学术

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On test time reduction using pattern overlapping, broadcasting and on-chip decompression

Published:2012-04 Issue: Volume: Page:
ISSN:
Container-title:2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
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Author:

Chloupek Martin,Novak Ondrej,Jenicek Jiri

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6213418/6219000/06219078.pdf?arnumber=6219078

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Industry Example to Reduce the Test Time by Optimizing Data Extration Method;2022 China Semiconductor Technology International Conference (CSTIC);2022-06-20

2. New scan compression approach to reduce the test data volume;IET Computers & Digital Techniques;2021-03-18

3. Thin wall injection‐overmoulding of polyamide 6/polypropylene multilayer parts: PA6/PP‐g‐ma interfacial adhesion investigations;Journal of Applied Polymer Science;2020-11-19

4. Test Time Optimization by Revisiting Notes in VLSI BIST Technique;3C Tecnología_Glosas de innovación aplicadas a la pyme;2020-03-23

5. Aggressive Exclusion of Scan Flip-Flops from Compression Architecture for Better Coverage and Reduced TDV: A Hybrid Approach;Journal of Low Power Electronics and Applications;2019-05-29

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