A CFI Verification System based on the RISC-V Instruction Trace Encoder

Author:

Zgheib Anthony1,Potin Olivier1,Rigaud Jean-Baptiste1,Dutertre Jean-Max1

Affiliation:

1. Mines Saint-Etienne, CEA, Leti, Centre CMP,Gardanne,France,F-13541

Publisher

IEEE

Reference37 articles.

1. CCFI-Cache: A Transparent and Flexible Hardware Protection for Code and Control-Flow Integrity

2. SoK: Eternal War in Memory

3. Instruction sets should be free: The case for risc-v;asanovi?;Technical Report UCB/EECS-2006–183 EECS Department,2014

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1. Internal State Monitoring in RISC-V Microarchitectures for Security Purpose;2024 IEEE 25th Latin American Test Symposium (LATS);2024-04-09

2. From Low-Level Fault Modeling (of a Pipeline Attack) to a Proven Hardening Scheme;Proceedings of the 33rd ACM SIGPLAN International Conference on Compiler Construction;2024-02-17

3. Experimental EMFI detection on a RISC-V core using the Trace Verifier solution;Microprocessors and Microsystems;2023-11

4. Fault Injection on Embedded Neural Networks: Impact of a Single Instruction Skip;2023 26th Euromicro Conference on Digital System Design (DSD);2023-09-06

5. CIFER: Code Integrity and control Flow verification for programs Executed on a RISC-V core;2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST);2023-05-01

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