Event-based verification of synchronous, globally controlled, logic designs against signal flow graphs
-
Published:1994
Issue:1
Volume:13
Page:122-134
-
ISSN:0278-0070
-
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
-
language:
-
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
Author:
Van Aelten F.,Allen J.,Devadas S.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Geometric Model Checking;Electronic Notes in Theoretical Computer Science;2002-04
2. From VHDL to efficient and first-time-right designs;ACM Transactions on Design Automation of Electronic Systems;1996-04