Analog NVM Synapse for Hardware-Aware Neural Network Training Optimization on 65nm CMOS TaOₓ ReRAM Devices
Author:
Affiliation:
1. College of Nanoscale Science & Engineering SUNY Polytechnic Institute,New York,USA
Funder
Air Force Research Laboratory
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10168132/10168044/10168155.pdf?arnumber=10168155
Reference25 articles.
1. Experimental Demonstration and Tolerancing of a Large-Scale Neural Network (165 000 Synapses) Using Phase-Change Memory as the Synaptic Weight Element
2. Short-Term Relaxation in HfOx/CeOx Resistive Random Access Memory With Selector
3. Optimizing Incremental Step Pulse Programming for RRAM Through Device–Circuit Co-Design
4. Optimization of Conductance Change in Pr1–xCaxMnO3-Based Synaptic Devices for Neuromorphic Systems
5. Fault-Tolerant Training with On-Line Fault Detection for RRAM-Based Neural Computing Systems
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