Low Power 10T SRAM Based Computing in Memory Macro Architecture for Binary MAC Operation of Edge AI Processors-Reference-Cited by-同舟云学术

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Low Power 10T SRAM Based Computing in Memory Macro Architecture for Binary MAC Operation of Edge AI Processors

Published:2024-04-11 Issue: Volume: Page:01-05
ISSN:
Container-title:2024 1st International Conference on Trends in Engineering Systems and Technologies (ICTEST)
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Author:

A V Arun¹,V Hareesh²,S A Ajay Nath³,M Sajeesh³

Affiliation:

1. Muthoot Institute of Technology & Science, APJ Abdul Kalam Technological University,Kerala,India

2. National Institute of Electronics & Information Technology,Calicut,Kerala,India

3. Model Engineering College, Kochi, India, Muthoot Institute of Technology & Science, APJ Abdul Kalam Technological University,Kerala,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10576062/10576051/10576118.pdf?arnumber=10576118

Reference16 articles.

1. 14.3 A 28nm SoC with a 1.2GHz 568nJ/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications

2. An Energy-Efficient Precision-Scalable ConvNet Processor in 40-nm CMOS

3. A Novel Software-Defined Convolutional Neural Networks Accelerator

4. Low Cost Convolutional Neural Network Accelerator Based on Bi-Directional Filtering and Bit-Width Reduction

5. MulNet: A Flexible CNN Processor With Higher Resource Utilization Efficiency for Constrained Devices

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