Low-Cost On-Chip Clock Jitter Measurement Scheme-Reference-Cited by-同舟云学术

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Low-Cost On-Chip Clock Jitter Measurement Scheme

Published:2015-03 Issue:3 Volume:23 Page:435-443
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Omana Martin,Rossi Daniele,Giaffreda Daniele,Metra Cecilia,Mak T. M.,Rahman Asifur,Tam Simon

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/7046457/06787039.pdf?arnumber=6787039

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. ADC Clock Jitter Measurement Based on Simple Coherent Sampling Algorithm;Journal of Physics: Conference Series;2022-11-01

2. HCDN: Hybrid-Mode Clock Distribution Networks;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-01

3. An improved BIJM circuit based on undersampling technique;IEICE Electronics Express;2018

4. Clock Jitter Reduction and Flat Frequency Generation in PLL Using Autogenerated Control Feedback;IEEE Transactions on Components, Packaging and Manufacturing Technology;2017-11

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