Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders-Reference-Cited by-同舟云学术

Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders

Published:2023-01 Issue:1 Volume:31 Page:142-146
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Gao Zhen¹^ORCID,Shi Jinchang¹,Liu Qiang¹^ORCID,Ullah Anees²^ORCID,Reviriego Pedro³^ORCID

Affiliation:

1. School of Electrical and Information Engineering, Tianjin International Engineering Institute and School of Microelectronics, respectively, Tianjin University, Tianjin, China

2. Department of Electronics Engineering, University of Engineering and Technology, Peshawar, Abbottabad, Pakistan

3. Departamento de Ingenería de Sistemas Telemáticos, Universidad Politécnica de Madrid, Madrid, Spain

Funder

NSF of China

ACHILLES

Agencia Estatal de Investigación

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/9998453/09969170.pdf?arnumber=9969170

Reference17 articles.

1. Design of FPGA-Implemented Reed–Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory

2. Concurrent Error Detection in Reed–Solomon Encoders and Decoders

3. Systematic MDS Erasure Codes Based on Vandermonde Matrices

4. Radiation hardened SEU tolerant Reed Solomon encoder and decoder

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