Funder
Department of Science and Technology (DST), Government of India
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Cited by
11 articles.
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1. Hyperblock Scheduling for Verified High-Level Synthesis;Proceedings of the ACM on Programming Languages;2024-06-20
2. A Testing Program and Pragma Combination Selection Based Framework for High-Level Synthesis Tool Pragma-Related Bug Detection;IEEE Transactions on Software Engineering;2024-04
3. Split Manufacturing Based Secure Hardware Design by BEOL Signal Selection In High Level Synthesis;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06
4. Verification-Driven Design for Asynchronous VLSI;2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC);2023-07-16
5. BLAST: Belling the Black-Hat High-Level Synthesis Tool;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022-11