All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme-Reference-Cited by-同舟云学术

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All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme

Published:2016-03 Issue:3 Volume:24 Page:1015-1024
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Jung Dong-Hoon,Ryu Kyungho,Park Jung-Hyun,Jung Seong-Ook

Funder

Samsung Electronics High-Speed SRAM Research and Development Project

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/7416268/7112541.pdf?arnumber=7112541

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Low-Jitter Harmonic-Free All-Digital Delay-Locked Loop for Multi-Channel Vernier TDC;Sensors;2021-12-31

2. A Wide-Range All-Digital Delay-Locked Loop for DDR1–DDR5 Applications;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-10

3. A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor;IEEE Access;2020

4. 0.293-mm2 Fast Transient Response Hysteretic Quasi- $V^{2}$ DC–DC Converter With Area-Efficient Time-Domain-Based Controller in 0.35- $\mu$ m CMOS;IEEE Journal of Solid-State Circuits;2018-06

5. An 8.52–11.34 GHz 0.34° Phase Error Quadrature Clock Generator with Time-Voltage-Time Convertor;2018 IEEE International Symposium on Circuits and Systems (ISCAS);2018-05

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