Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures

Author:

Liu Dajiang,Yin Shouyi,Peng Yu,Liu Leibo,Wei Shaojun

Funder

China Major Science and Technology (S&T) Project

National High Technologies Research Program, China

National Natural Science Foundation of China

International S&T Cooperation Project

Tsinghua Indigenous Research Project

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. E2EMap: End-to-End Reinforcement Learning for CGRA Compilation via Reverse Mapping;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02

2. Towards High-Quality CGRA Mapping with Graph Neural Networks and Reinforcement Learning;Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design;2022-10-30

3. An Analysis of Mapping Polybench Kernels to HPC CGRAs;2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW);2022-05

4. Mapping-Aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning;IEEE Transactions on Parallel and Distributed Systems;2022-05-01

5. OpenCGRA: Democratizing Coarse-Grained Reconfigurable Arrays;2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP);2021-07

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