Statistical Run-Time Verification of Analog Circuits in Presence of Noise and Process Variation

Author:

Narayanan Rajeev,Seghaier Ibtissem,Zaki Mohamed H.,Tahar Sofiene

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Mating Sensitivity Analysis and Statistical Verification for Efficient Yield Estimation;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2020-02

2. Statistically Validating the Impact of Process Variations on Analog and Mixed Signal Designs;Proceedings of the 25th edition on Great Lakes Symposium on VLSI;2015-05-20

3. A qualitative simulation approach for verifying PLL locking property;Proceedings of the 24th edition of the great lakes symposium on VLSI - GLSVLSI '14;2014

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