A High-Speed Low-Noise Comparator With Auxiliary-Inverter-Based Common Mode-Self-Regulation for Low-Supply-Voltage SAR ADCs
Author:
Affiliation:
1. College of Electronics and Information Engineering, Tongji University, Shanghai, China
Funder
National Natural Science Foundation of China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx7/92/9998453/09969998.pdf?arnumber=9969998
Reference12 articles.
1. The StrongARM Latch [A Circuit for All Seasons]
2. A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture
3. A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise
4. Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures
5. An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier
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