Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM-Reference-Cited by-同舟云学术

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Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM

Published:2019-10 Issue:10 Volume:27 Page:2413-2422
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Kim Suk Min^ORCID,Song Byungkyu,Jung Seong-Ook^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/8848667/08744261.pdf?arnumber=8744261

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Improved Parasitic Capacitance-Predictively Aware DTCO: Enhanced Cell Efficiency With Manufacturability and Scalability for 4F² VCT-Based DRAM;IEEE Transactions on Electron Devices;2024-07

2. HiFi-DRAM: Enabling High-fidelity DRAM Research by Uncovering Sense Amplifiers with IC Imaging;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29

3. Low-Power Single Bitline Load Sense Amplifier for DRAM;Electronics;2023-09-25

4. An Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Boosted Internal-Voltage-Difference;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-09

5. An asymmetrically controlled sense amplifier with boosted sensing voltage difference for low-voltage and high-density DRAM;Microelectronic Engineering;2023-05

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