Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS-Reference-Cited by-同舟云学术

Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS

Published:2024-01 Issue:1 Volume:32 Page:116-127
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Yan Aibin¹^ORCID,Wang Litao¹,Cui Jie¹^ORCID,Huang Zhengfeng²^ORCID,Ni Tianming³^ORCID,Girard Patrick⁴^ORCID,Wen Xiaoqing⁵^ORCID

Affiliation:

1. School of Computer Science and Technology, Anhui University, Hefei, China

2. School of Microelectronics, Hefei University of Technology, Hefei, China

3. School of Integrated Circuits, Anhui Polytechnic University, Wuhu, China

4. LIRMM, University of Montpellier/CNRS, Montpellier, France

5. Graduate School of Computer Science and Systems Engineering, Kyushu Institute of Technology, Fukuoka, Japan

Funder

National Natural Science Foundation of China

State Key Laboratory of Computing Institute, Chinese Academy of Sciences

Anhui Provincial Universities through the Outstanding Young Talent

Distinguished Young Scholar Fund of Anhui Province

Key Research and Development Projects in Anhui Province

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

Reference24 articles.

5. Co/Ni based p-MTJ stack for sub-20 nm high density stand alone and high performance embedded memory application;Kar

Cited by 24 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献