Cerebron: A Reconfigurable Architecture for Spatiotemporal Sparse Spiking Neural Networks-Reference-Cited by-同舟云学术

Cerebron: A Reconfigurable Architecture for Spatiotemporal Sparse Spiking Neural Networks

Published:2022-10 Issue:10 Volume:30 Page:1425-1437
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Chen Qinyu¹^ORCID,Gao Chang²^ORCID,Fu Yuxiang³^ORCID

Affiliation:

1. Institute of Photonic Chips, University of Shanghai for Science and Technology, Shanghai, China

2. Department of Microelectronics, Delft University of Technology, Delft, The Netherlands

3. School of Electronic Science and Technology, Nanjing University, Nanjing, China

Funder

Science and Technology Commission of Shanghai Municipality

Shanghai Frontiers Science Center Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

Reference55 articles.

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