Funder
JSPS KAKENHI
VLSI Design and Education Center (VDEC), The University of Tokyo, in collaboration with Synopsys, Inc., and Cadence Design Systems, Inc.
JST CREST
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Cited by
28 articles.
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1. RoDMap: A Reserve-on-Demand Mapper for Spatially-Configured Coarse-Grained Reconfigurable Arrays;Proceedings of the 53rd International Conference on Parallel Processing;2024-08-12
2. Exploration of Trade-offs Between General-Purpose and Specialized Processing Elements in HPC-Oriented CGRA;2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS);2024-05-27
3. TransMap: An Efficient CGRA Mapping Framework via Transformer and Deep Reinforcement Learning;2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW);2024-05-27
4. Mapping Enumeration for Multi-Context CGRAs Using Zero-Suppressed Binary Decision Diagrams;2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM);2024-05-05
5. E2EMap: End-to-End Reinforcement Learning for CGRA Compilation via Reverse Mapping;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02