A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique
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Published:2017-01
Issue:1
Volume:25
Page:344-353
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ISSN:1063-8210
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Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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language:
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Short-container-title:IEEE Trans. VLSI Syst.
Author:
Song Junyoung,
Lee Hyun-Woo,
Hwang Sewook,
Kim ChulwooORCID
Funder
National Research Foundation of Korea Grant funded by the Korea Government (Ministry of Science, ICT, and Future Planning)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software