A 10-Gb/s Eye-Opening Monitor Circuit for Receiver Equalizer Adaptations in 65-nm CMOS-Reference-Cited by-同舟云学术

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A 10-Gb/s Eye-Opening Monitor Circuit for Receiver Equalizer Adaptations in 65-nm CMOS

Published:2020-01 Issue:1 Volume:28 Page:23-34
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Lin Yu-Chuan^ORCID,Tsao Hen-Wai^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/8945454/08825542.pdf?arnumber=8825542

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Evaluation of Multi-Valued Data Transmission in Two-Dimensional Symbol Mapping using Linear Mixture Model;IEICE Transactions on Information and Systems;2024-08-01

2. A 16-Gb/s 3-tap adaptive DFE in 12-nm FinFET CMOS technology;Microelectronics Journal;2024-07

3. A 4-26 Gbaud Configurable Multi-Mode Non-Uniform EOM with Improved Twin PI for High-Speed Wireline Communication Achieving 3-μs EW/EH Evaluation and 0.99-R² Accuracy;2024 IEEE Radio Frequency Integrated Circuits Symposium (RFIC);2024-06-16

4. Equalization for Compensation of Intersymbol Relationship of Multi-Valued Signaling Using Two-Dimensional Symbol Mapping;2024 IEEE 54th International Symposium on Multiple-Valued Logic (ISMVL);2024-05-28

5. A 32Gb/s Equalizer with Adaptive T-Coil Input Matching and Fullrate DFE in 28nm CMOS;2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA);2024-04-22

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